; Clock Generator Module / Phase-Locked Loop (PLL) routines. ; Copyright © 2000-2004 by David Cook. ; www.robotroom.com ; 2000/09/04 DAC Written. ; 2004/01/04 DAC Added additional bus rate. ; Made sure no ADC rate exceeded 1.048 MHz, per REV 5 GP32 guide. ; Added some constants. ; Changed some formatting. ;******************************************** ;* * ;* Equates * ;* * ;******************************************** ; Remove the leading semicolon to uncomment the following equates if a gpregs.inc file ; isn't included in your project or is missing these definitions. ;scbr equ $0019 ; ;pctl equ $0036 ;PLLIE equ 7 ;PLLON equ 5 ;BCS equ 4 ; ;pbwc equ $0037 ;AUTO equ 7 ;LOCK equ 6 ; ;pmsh equ $0038 ;pmsl equ $0039 ;pmrs equ $003A ;pmds equ $003B ; ;adclk equ $003E ; ;ADIV2. equ %10000000 ;ADIV1. equ %01000000 ;ADIV0. equ %00100000 ;ADICLK. equ %00010000 ;******************************************** ;* * ;* PLLSetup * ;* * ;******************************************** ; Example routine which sets up maximum bus speed. I call this early on startup. ; IN: A, H, and X are ignored. ; OUT: A, H, and X are unchanged. PLLSetup: pshx pshh ldhx #BUS8200192 jsr PLLset pulh pulx rts ;******************************************** ;* * ;* PLLSet * ;* * ;******************************************** ; PLLSet sets the PLL, ADC, and SCI (9600 baud) to the correct rates ; based on which address in the table below is stored in HX register. ; IN: A is ignored. HX is bus rate table address. ; OUT: A, H, X, and CCR are unchanged. PLLSet: psha pshx pshh tpa psha sei ; Don't allow interrupts while ; we're modifying the clock rate bclr PLLIE,pctl ; Disable PLL Lock interruptions ; (probably unnecessary). bclr BCS,pctl ; Select external reference as base clock ; because we're turning off the PLL. bclr PLLON,pctl ; Turn off the PLL so we can configure it. mov x+,pctl ; Program P (PRE1, PRE0) and E (VPR1, VPR0). mov x+,pmrs ; Program L (VRS7-VRS0). mov x+,pmsh ; Program N most-significant byte. mov x+,pmsl ; Program N least-significant byte. mov #1,pmds ; Program R to 1. bset AUTO,pbwc ; Enable automatic bandwidth control. bset PLLON,pctl ; Turn on PLL. mov x+,scbr ; Program SCI Baud Rate register. ; Be sure to also mov ; {whatever|SCIBDSRC.},config2 ; to select the internal bus as ; baud rate source ; wherever you initialize to ; write-once config2 ; register in your code. ; The Timebase Module (TBM) is connected to CGMXCLK (crystal frequency) ; and as such is not altered by the configured bus speed. ; So, no change is necessary to the TBM. mov x+,adclk ; Program ADC clock register. ; Also note that the bus clock is also ; selected as the input clock source (ADICLK=1) ; by this mov instruction. ; Comment out the next instruction if your application ; doesn't require clock stability before continuing. brclr LOCK,pbwc,* ; Wait for PLL to lock. bset BCS,pctl ; Select PLL as base clock. pula tap ; Restore interrupts only if they were enabled. pulh pulx pula rts ;******************************************** ;* * ;* PLLSet Bus Rate Table * ;* * ;******************************************** ; Table of different bus rates when using a 32.768 kHZ crystal. ; ldhx #BUSxxxxxxx before calling PLLSet. ; To save FLASH space, feel free to comment out any rates you don't use. ; The SCI, ADC, and TIM divide from the final BUS clock, not the original clock speed. ; (Actually the config register determines the SCI source of BUS or original.) ; The TBM divides from the original clock speed, not the BUS speed. ; Because this uses the PLL, the internal bus rate must always be used (ADICLK.). ADCI_DIV__1 equ {ADICLK.} ADCI_DIV__2 equ {ADIV0.|ADICLK.} ADCI_DIV__4 equ {ADIV1.|ADICLK.} ADCI_DIV__8 equ {ADIV1.|ADIV0.|ADICLK.} ADCI_DIV_16 equ {ADIV2.|ADICLK.} BUS1228800: ; 1.2288 MHz bus ; (Matches the 4.9152 MHz oscillator programming board.) db $00 ; P & E db $80 ; L dw $0096 ; N db %00000001 ; Serial (SCI) = 9600 baud db ADCI_DIV__2 ; ADC clock = 0.6144 MHz BUS2007040: ; 2.00704 MHz bus db $00 ; P & E db $D1 ; L dw $00F5 ; N db %00010000 ; Serial (SCI) = 10453 baud (Ick! Unusable) db ADCI_DIV__2 ; ADC clock = 1.00352 MHz BUS2457600: ; 2.4576 MHz bus db $01 ; P & E db $80 ; L dw $012C ; N db %00000010 ; Serial (SCI) = 9600 baud db ADCI_DIV__4 ; ADC clock = 0.6144 MHz BUS2506752: ; 2.506752 MHz bus db $01 ; P & E db $83 ; L dw $0132 ; N db %00000010 ; Serial (SCI) = 9792 baud db ADCI_DIV__4 ; ADC clock = 0.626688 MHz BUS4005888: ; 4.005888 MHz bus db $01 ; P & E db $D1 ; L dw $01E9 ; N db %00010001 ; Serial (SCI) = 10432 baud (ick! unusable!) db ADCI_DIV__4 ; ADC clock = 1.001472 MHz BUS4915200: ; 4.9152 MHz bus db $02 ; P & E db $80 ; L dw $0258 ; N db %00000011 ; Serial (SCI) = 9600 baud db ADCI_DIV__8 ; ADC clock = 0.6144 MHz BUS5005312: ; 5.005312 MHz bus db $02 ; P & E db $82 ; L dw $0263 ; N db %00000011 ; Serial (SCI) = 9776 baud db ADCI_DIV__8 ; ADC clock = 0.625664 MHz BUS7372800: ; 7.3728 MHz bus db $02 ; P & E db $C0 ; L dw $0384 ; N db %00010010 ; Serial (SCI) = 9600 baud db ADCI_DIV__8 ; ADC clock = 0.9216 MHz BUS8003584: ; 8.003584 MHz bus db $02 ; P & E db $D0 ; L dw $03D1 ; N db %00110000 ; Serial (SCI) = 9620 baud db ADCI_DIV__8 ; ADC clock = 1.000448 MHz BUS8200192: ; 8.200192 MHz bus db $02 ; P & E db $D6 ; L dw $03E9 ; N db %00110000 ; Serial (SCI) = 9856 baud (borderline) ; 9938 is 3.53% too fast maximum. db ADCI_DIV__8 ; ADC clock = 1.025024 MHz